An FPGA comparative study of high‐level and low‐level combined designs for HEVC intra, inverse quantization, and IDCT/IDST 2D modules

Abstract

SummaryTwo main design methods are currently widely adopted in dealing with complex signal processing algorithms. The first method is based on low‐level synthesis (LLS), which consists in writing the hardware description languages (HDL) code manually. However, the second method, called high‐level synthesis (HLS), generates the register transfer level (RTL) description automatically starting from a high‐level description language. The challenge in this paper was to study the impact of both design methods on such a complex application as the High Efficiency Video Coding (HEVC) decoder. With this end in view, we analyzed the complexity of the HEVC decoder in a software environment using version 10 of the HEVC test model (HM) reference software to determine which portions tended to get optimized. The combined architecture for the intra prediction (IP) and the inverse quantization and transform (IQ/IT) was then implemented in hardware using HLS and LLS. The findings obtained under the Xilinx Zynq 7045‐based field‐programmable gate array (FPGA) proved that the HLS implementation enabled a gain of about 80% in Look Up Table (LUTs) with an increase of 93% in DSP blocks compared with LLS implementation. Yet only the LLS solution could achieve the real‐time decoding of 4K@26fps instead of the 1080p@24fps by the HLS design.