Abstract
An all-digital voltage-controlled oscillator (VCO)-based second-order multi-stage noise-shaping (MASH) ΔΣ time-to-digital converter (TDC) is presented in this paper. The prototype of the proposed TDC was implemented on an Altera Stratix IV FPGA board. In order to improve the performance over conventional TDCs, a multirating technique is employed in this work in which higher sampling rate is used for higher stages. Experimental results show that the multirating technique had a significant influence on improving signal-to-noise ratio (SNR), from 43.09 dB without multirating to 61.02 dB with multirating technique (a gain of 17.93 dB) by quadrupling the sampling rate of the second stage. As the proposed design works in the time-domain and does not consist of any loop and calibration block, no time-to-voltage conversion is needed which results in low complexity and power consumption. A built-in oscillator and phase-locked loops (PLLs) of the FPGA board are utilized to generate sampling clocks at different frequencies. Therefore, no external clock needs to be applied to the proposed TDC. Two cases with different sampling rates were examined by the proposed design to demonstrate the capability of the technique. It can be implied that, by employing multirating technique and increasing sampling frequency, higher SNR can be achieved.
Highlights
In many applications such as all-digital phase-locked loops (ADPLLs) [1], chemical sensors readout [2], frequency synthesizers [3,4,5,6], and time-of-flight (ToF) systems [7], time-to-digital converters (TDCs) play an important role by measuring a time interval
We propose a 16-bit continuous-time TDC that takes advantage of employing gated switched-ring oscillators (GSROs) quantizer to suppress quantization error leakage and at the same time benefits from a multirating technique to improve signal-to-noise ratio (SNR) further over conventional TDCs
This section describes the theoretical background of ∆ TDCs using a GSRO and the multirating technique to give an overview of the proposed architecture
Summary
In many applications such as all-digital phase-locked loops (ADPLLs) [1], chemical sensors readout [2], frequency synthesizers [3,4,5,6], and time-of-flight (ToF) systems [7], time-to-digital converters (TDCs) play an important role by measuring a time interval. To achieve finer time-resolution a 1-1 multi-stage noise-shaping (MASH) TDC can be formed by cascading two SRO-TDCs using two identical SROs, and the difference in the SROs operating frequencies results in systematic error which requires calibration unit to compensate the error This takes a long settling time and suffers from additional power consumption and chip area [19]. 1-1 MASH ∆ TDC has been proposed in [21] It exploits a digital ring oscillator in the second stage, a switched-capacitor VCO is used in its first stage that suffers from non-linearity and low operating frequency and because of analog implementation occupies high chip area and consumes excessive power.
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
