Abstract
This paper describes a noise filtering method for ¿¿ fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the ¿¿ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR ¿¿ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz ¿¿ fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> PLL is implemented in 0.18 ¿m CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.
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