Abstract

In this paper, a charge sheet surface potential based model for strained-Si nMOSFETs is presented and validated with numerical simulation. The model considers sub band splitting in the 2-DEG at the top heterointerface in SiGe layer and also the dependence of electron concentration at heterointerface with the gate oxide. The model is scalable with strained-Si material parameters with physically derived flat-band voltages. An explicit relation for surface potential as a function of terminal voltages is developed. The model is derived from regional charge-based approach, where regional solutions are physically derived. The model gives an accurate description of drain current both in the weak and strong inversion regions of operation. The results obtained from the model developed are benchmarked with commercial numerical device simulator and is found to be in excellent agreement.

Highlights

  • As conventional Si MOSFETs are scaled into nanometer regime, maintaining performance enhancement beyond 90-nm technology node is becoming extremely difficult

  • The model is scalable with strained-Si material parameters with physically derived flat-band voltages

  • We report on the surface potential based analytical model for drain current of heterostructure strained-Si n-MOSFETs considering the carrier transport at the strained-Si/silicon germanium (SiGe) heterointerface as well as at strained-Si/SiO2 interface

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Summary

Introduction

As conventional Si MOSFETs are scaled into nanometer regime, maintaining performance enhancement beyond 90-nm technology node is becoming extremely difficult. Among the possible solutions, engineered substrates, in particular, substrate-induced strained silicon (strained-Si) has been identified as very promising for channel engineered MOSFETs as it improves the CMOS performance [2,3,4,5,6]. In this case, the strain is introduced at the substrate level before the transistor is built (opposite to process-induced strain currently being used in 45 nm technology node). Subband degeneracy in both the conduction and valence bands and reducing the band gap [13,14]

Strained-Si CMOS Technology
Device Structure and Operation of Strained-Si n-MOSFETs
Position of Fermi Level in Strained-Si Layer
Sheet Electron Concentrations in Channels as Functions of VG
SSi qNSiGe LDtSSi SiGe qNSiGe L2D 2 SiGe
Drain-Current Model
SiGe ds at the 2-DEG in
SSi ds
Results and Discussion
Conclusions
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