An experimental study of the source/drain parasitic resistance effects in amorphous silicon thin film transistors

Abstract

The effect of source/drain (S/D) parasitic resistance has been experimentally investigated for amorphous silicon (a-Si:H) thin film transistors (TFTs). In general, the apparent field effect mobility decreases with decreasing channel length. However, the apparent threshold voltage is relatively constant. This may be attributed to an ohmic parasitic resistance due to the use of ion-implanted n+ S/D regions. Self-consistent results were obtained from both TFTs and from independent test structures for the TFT parasitic resistance, contact resistance, and sheet resistance. The results showed that the current spreading under the S/D regions is most critical in determining the magnitude of the total parasitic resistance. In this regard, both the S/D ion implantation and the S/D to gate overlap reduce the total parasitic resistance. Finally, the parasitic resistance is modeled as a gate voltage-modulated channel resistance, under the gate overlap, in series with a constant minimum contact resistance.