An experimental multi-processor architecture for small business applications

Abstract

Outlines the design of an experimental multi-processor system intended for such small business applications. Its architecture is highly modular, both in hardware and software, permitting microprocessors to realize this expanding capability. In the simplest configuration, the CPU comprises a master and a single slave microprocessor. As the demand on the computer increases, additional slaves can be added until, in the limit, the master functions primarily as the system scheduler. The organization and control of both the hardware and software is presented. The methods used for bus sharing, microprocessor interlacing, and timing are discussed, as well as the techniques used to achieve high speed interrupt response needed to control point of sale terminals, perpetual inventory, and other real time operations. The structure of the system executive, and the mechanism used to allocate system resources and control the execution and interaction of parallel system tasks is described in detail.