An example of fault site localization on a 0.18 μm CMOS device with combination of front and backside techniques

Abstract

This paper describes a failure analysis on a 0.18 μm CMOS device. To find out fault mechanism, combination of several fault localization techniques that are both front and backside were utilized. Fault mechanism is discussed, including the relation between the results of these techniques and physical layout with circuit information. In this case, the failure device had these features: multi-metallization process with dummy fill metals, low supply voltage, and non-function with high I DD leakage. These features made verifying the fault mechanism very difficult. We provide an approach of voltage contrast method with FIB milling techniques. This approach enabled to probe inner nodes in the multi-metallization device and to verify the fault mechanism. We also discuss the verification with circuit simulation and the root cause in detail.