An event-driven 8-bit ADC with a segmented resistor-string DAC

Abstract

An event-driven, clock-free analog-to-digital converter (ADC) based on a continuous-time delta modulation technique is presented in this work. The ADC output is a digital datum, continuous in time. The ADC system employs an unbuffered, area efficient segmented resistor-string digital-to-analog converter (DAC). Simulation results of the high level model of an 8-bit event-driven DM ADC system is presented. Numbers in terms of component savings (number of resistors and switches in the DAC and D flip-flops in the bi-directional shift registers) as well as a comparison in component reduction with prior art are presented. Component savings of nearly 87% is observed for the 8-bit ADC system utilizing a segmented resistor-string DAC architecture. The achieved SNDR and SFDR for the 8-bit ADC is 60.3 dB and 66.0 dB, respectively.