Abstract
This article introduces a digitally intensive event-driven quasi-level-crossing (quasi-LC) delta-modulator analog-to-digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks, in which minimizing the average sampling rate for sparse input signals can significantly reduce the power consumed in data transmission, processing, and storage. The proposed AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive-approximation-register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The proposed modulator achieves data compression by means of a globally signal-dependent average sampling rate and achieves AR through a digital multi-level comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in the conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of 3 at the edge of the modulator’s signal bandwidth. The proposed modulator is fabricated in 28-nm CMOS and achieves a peak SNDR of 53 dB over a signal bandwidth of 1.42 MHz while consuming 205 $\mu \text{W}$ and an active area of 0.0126 mm2.
Highlights
This article introduces a digitally intensive eventdriven quasi-level-crossing delta-modulator analogto-digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks, in which minimizing the average sampling rate for sparse input signals can significantly reduce the power consumed in data transmission, processing, and storage
The proposed modulator exploits an alternative method of performing level crossing (LC) sampling, which is reasonably insensitive to the effects of absolute timing errors, here represented by the absolute time jitter of the sub-analog-to-digital converter (ADC) clock, which is reasonably lower than the loop delay variation (tL) and not signal-dependent
As clock signal for the residue quantizer (CLK) is applied to the residue quantizer, the signal bandwidth of the proposed quasi-LC delta modulator is constrained by the fact that the maximum voltage shift that the feedback DAC is able to provide within TCLK corresponds to the coarsest resolution allowed by the AR scheme, max
Summary
W IRELESS sensor devices underpin the broad ecosystem of the Internet of Things (IoT), in which the RF transmitter (TX) and digital signal processor (DSP) dominate the power consumption budget. In this article, which is an extension of [14], we propose an AR delta modulator that quantizes its voltage residue VRES by means of a low-resolution sub-ADC (hereafter referred to as “residue quantizer”). This allows a straightforward implementation of LC and AR algorithms in the digital domain, which can be realized as readily synthesizable logic. From conventional LC ADCs, the proposed delta modulator exploits the LC algorithm in the sampled digital domain, which is the reason for adopting the “quasi-LC” terminology. It uses a 16-bit counter in the FPGA operating at a frequency with an OSR of 500, which is not a practical solution for an IoT node
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