AN EVALUATION ON THE OPERATIONAL EFFICIENCY OF TAIWANESE SEMICONDUCTOR IC INDUSTRY

Abstract

The purpose of this research is to elaborate a three-stage hybrid measure data envelopment analysis (DEA) with meta-frontier model, and then estimate the technical efficiency of Taiwanese semiconductor integrated circuit (IC) companies by using data from 2005 to 2016 on 92 firms. The study divided the Taiwanese semiconductor IC companies into two groups (IC design and IC manufacturing/packaging/testing) based on their different production characteristics and using the concepts of DEA meta-frontier models proposed by [O’Donnell, CJ, DP Rao, GE Battese (2008). Meta-frontier frameworks for the study of firm-level efficiencies and technology ratios. Empirical Economics, 34(2), 231–255] to estimate their efficiencies. The empirical results of this study show that the adjustment range of the average meta-efficiency values of all firms is higher than the adjustment range of the financial turbulent in 2007–2009 and 2011–2013. Second, before and after the adjustment, the distribution of the meta-technology ratio (MTR) changed slightly. The main reason may be that the global economic recession triggered by the 2007–2009 global financial tsunami and the 2011–2013 European debt crisis offset the impact of technological progress. Finally, under the considerations of environmental factors, the ratio of export to total sales, the degree of diversification, research and development spillover effects and the ratio of investment to mainland China are the main determinants influencing the operational performance of Taiwanese semiconductor IC firms and the impacts on MTR.