An error-compensated piecewise linear logarithmic arithmetic unit for phong lighting acceleration

Abstract

This paper presents an error compensated piecewise linear logarithmic arithmetic unit for Phong lighting hardware acceleration. Two novel error compensation techniques have been applied to differentiate finer bounds within piecewise linear (PWL) approximation intervals to achieve a lower absolute mean error rate with minimal increment in resource costs. Area/power/error performances of the logarithmic unit designs are presented for the proposed topologies applied to a five-interval base-2 PWL logarithm approximation circuit in comparison to its baseline counterpart. In addition, the design is applied to a single-cycle Phong lighting hardware accelerator and evaluated for graphical estimation accuracy at the system-level.