An Enhanced Transfer Delay-Based Frequency Locked Loop for Three-Phase Systems With DC Offsets

Abstract

In this paper, an enhanced transfer delay-based frequency locked loop (ETD-FLL) is proposed to estimate the frequency, the positive- and negative-sequence voltage with strong immunity against dc offsets. By analyzing the relationship between the grid voltage and its transfer delay signals, a linear regression model is established, which is related to the unknown parameters-the dc offsets and grid frequency. Accordingly, the problem of positive- and negative-sequence voltage detection is transformed as the issue of parameter identification based on the obtained model. Then, the normalized gradient method is proposed to estimate the unknown parameters in the established model and finally achieve the detection of positive- and negative-sequence voltage. A mathematic proof is provided to indicate that the proposed method has good steady-state accuracy and strong dc offset immunity. In addition, the proposed ETD-FLL has fast dynamics due to its transfer delay structure. The experimental results further confirm that the proposed method has good performance in terms of dynamics and dc offset immunity.