An enhanced Gate Diffusion Input technique for low power applications

Abstract

Power consumption in data manipulation strongly depends on the performance of full adder which is the primary block from which any larger circuits could be stacked. This paper addresses logic swing degradation in Gate Diffusion Input (GDI) and the glitches caused by the corresponding technique during run time. The effects of glitches at different operating frequencies were analysed. An Enhanced Gate Diffusion Input (EGDI) based full adder with focus on EGDI logic cells and its realizations has been proposed. EGDI based full adder consumes maximum average power of 40.4 pW and minimum average power of 0.595 pW for the operating frequency of 5 KHz and 500 KHz respectively. When GDI and CMOS are compared with EGDI technique, it consumes 0.01% less power than GDI technique at f0 = 50 KHz and f0 = 500 KHz respectively. The transistor level conventional simulations and power consumption have been evaluated using an Analog Device’s LTSPICE-XVII simulator with 180 nm TSMC technology libraries.