An enhanced compact waffle MOSFET with low drain capacitance from a standard submicron CMOS technology

Abstract

A compact waffle MOSFET using an enhanced waffle-layout strategy is presented together with the comparison with the traditional waffle design. The enhanced compact waffle MOSFET’s have been fabricated using a 0.35-μm standard CMOS process. The true compactness of the enhanced compact waffle design is verified by the experimental results which show a reduction of about 25% in drain diffusion capacitance per unit transistor width but without any performance compromise in driving current, transconductance and subthreshold characteristics of the waffle MOSFET. With its compactness, the enhanced waffle layout uses about 35% less active device area compared with the multifinger counterpart. All these benefits are obtained without any extra processing cost.