An Energy Efficient, Mismatch Tolerant Offset Compensating Hybrid MTJ/CMOS Magnetic Full Adder

Abstract

The miniaturization of CMOS have lead to high leakage and process variation at sub-micron technology. Hybrid circuits including CMOS and magnetic tunnel junction (MTJ), a spintronic device have been put forward to conquer aforesaid limitations. MTJs have appeared to be most assuring candidates owing to it’s compatibility with CMOS and almost zero leakage power. In this brief an offset compensating magnetic full adder (OCMFA) (a hybrid circuit of CMOS and MTJ) has been proposed, which compensates the offset voltage occurring due to process variation and mismatch. The proposed OCMFA compensates the offset voltage in the precharge mode by pre-charging the outputs associated with high resistance branch at a higher voltage and that with lower resistance branch at a lower voltage. The asymmetrical pre-charging of output nodes is assisted by the write current, to provide input to MTJs and load connected diodes. Thus, it is robust against process variation and upgrades the performance of MFA. Power, delay, variability, and corner analysis are performed utilizing UMC 40nm CMOS technology kit at the cadence virtuoso platform and the compact model of perpendicular magnetic anisotropy (PMA) MTJ. This brief contributes in the reliability analysis of proposed MFA with the earlier reported MFA. The proposed OCMFA provides 65% lower PDP and shows 84.6% higher reliability as compared to conventional precharge sense amplifier based magnetic full adder (PCSA-MFA).