An Energy-Efficient Hybrid Tunnel FET based STT-MRAM Memory Cell Design at Low VDD

Abstract

ABSTRACT Perpendicular Magnetic Anisotropy-based Magnetic Tunnel Junction (PMA-MTJ) and Spin Transfer Torque Magnetic Random-Access Memory (STT-MRAM) have attracted wide attention among the next-generation Non-Volatile Memory (NVM) technologies due to low leakage and high-density characteristics for embedded memory architectures. However, STT-MRAM-based memory cells are not energy efficient with CMOS scaling at scaled supply voltages. This paper presents a novel energy-efficient Hybrid TFET (1 T: Hetero-junction TFET, 1 T: Homo-junction TFET)/STT-MRAM cell that explores p-i-n forward current of Tunnel FET. The proposed hybrid memory cell demonstrates ~27.3% energy efficiency over equivalent 1 T FinFET/STT-MRAM cell, 16.75% energy efficiency over equivalent 1 T Homo-junction TFET/STT-MRAM cell and 24.3% energy efficiency over equivalent 1 T Hetero-junction TFET/STT-MRAM cell at VDD = 0.5 V.