Abstract
A subthreshold ECG processor in 45-nm IBM SOI CMOS is designed to operate at the minimum energy operating point (MEOP). Statistical error compensation (SEC) is employed to further reduce energy (Emin) at the MEOP. SEC is shown to reduce Emin by 28% compared with the conventional (error-free) case while maintaining acceptable beat-detection performance. SEC enables the supply voltage to be scaled to 15% below its critical value at MEOP, while compensating for a 58% precorrection error rate pe. These results represent an improvement of 19× in beat-detection performance and 600× in pe over conventional (error-free) systems. The prototype IC consumes 14.5 fJ/cycle/1k-gate and exhibits 4.7× better energy efficiency than the state of the art while tolerating 16× more voltage variations.
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