Abstract
Editor's note:As part of their ongoing work with the National Science Foundation (NSF) Center for High-Performance Reconfigurable Computing (CHREC), the authors are developing a complete tool chain for FPGA-based acceleration of scientific computing, from early-stage assessment of applications down to rapid routing. This article provides an overview of this tool chain.—George A. Constantinides (Imperial College London) and Nicola Nicolici (McMaster University)
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