An Encrypt and Decrypt Algorithm Implementation on FPGAs

Abstract

Internet Protocol Security (generally shortened to IPSec) is a framework of open standards that provides data confidentiality, data integrity, and data authentication between participating peers at the IP layer. The Data Encryption Standard(DES) is used to encrypt and decrypt packet data at IP layer; it turns clear text into cipher text via an encryption algorithm. The decryption algorithm on the remote end restores clear text from cipher text. Shared secret keys enable the encryption and decryption. DES uses a 56-bit key, ensuring high-performance encryption, Field -programmable gate arrays(FPGA) are reconfigurable digital integrated circuits that in the past have proven to provide high performance and low cost for cryptographic application. In this paper, FPGA is used for carrying out the fully pipeline, fully parallel DES coding and decoding algorithm because it exploits inherent parallelism in the algorithms and matches very well for operations required for private key. Finally, this paper designs core architecture of FPGA for two-round DES algorithm and introduces the flow diagram of DES algorithm in detail. Moreover, some experiment are carried out to study plaintext/ciphertext correlation and statistical characteristic, the results show this method is effective and the proposed cipher has higher security, faster encryption and lower computation expense as well as other good cryptographic properties. Finally, a performance analysis to cryptanalysis is presented by determining the most effective FPGA chip to perform large scale cryptanalysis through a speed survey of various FPGA chips.