An Emulated Digital CNN Implementation

Abstract

A new emulated digital CNN Universal Machine chip architecture is introduced and the main steps of the design process are shown in this paper. One core processor can be implemented on 2 × 2 mm^2 silicon area with a 0.35 μm CMOS technology. Assuming an array of 24 processors on a chip, its speed is 1ns/virtual cell/CNN iteration with 12 bit precision. This enables the execution of over five hundred 3 × 3 convolution operations on each frame of a 240 × 320-pixel 25 fps digital image flow. Another new feature of the design is its variable precision capability. This allows the user to trade off precision for speed. The architecture supports some non-linear filter implementation as well.