Abstract
As the semiconductor industry is moving down to deep-sub micron era (below 45nm), Well Proximity Effect (WPE) is causing significant variations in device performance. This may impact the functionality and performance of circuit designs in highly scaled CMOS technologies. In this work, we have studied the impact of WPE on standard cells and propose an empirical delta-delay model for an inverter in 28nm technology node as a function of well to poly edge distance. Our model can be extended for other standard cells and can be used for context aware standard cell library characterization considering WPE.
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