Abstract
Age related macular degeneration and retinitis pigmentosa are two most common cause for loss of sight. In this paper an architecture of a processor has been described for 64 electrode implantable retinal prosthesis chip. The processor takes serial data and generates PWM signals according to the serially received data. This paper describes basically the design and implementation of a UART (Universal Asynchronous Receiver and Transmitter) module, dual port RAM module, a controller module and PWM signal generator module. The processor has been designed with Verilog HDL and synthesized on Altera DE0 nano board. Singaltap logic analyser has been used for the debugging purpose.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
