An electronic packaging design for reduction of thermal interface resistance

Abstract

Thermal resistances between chips and their associated copper heat spreaders, and between the copper heat spreaders and the fin and fan assemblies, have a dominant impact on the overall heat flow out of the chip (e.g., microprocessor). Thermal interface materials (TIM) introduces a bulk resistance and two interface resistances, which for commercially available TIMs add up to a total thermal resistance on the order of 10/sup -4/ to 10/sup -5/ K-m/sup 2//W. While there has been a great deal of improvement in TIM thermal characteristics for the past decade, it appears that there are fundamental barriers to further reduction in the thermal resistance of TIM beyond 10/sup -4/ to 10/sup -5/ K-m/sup 2//W. Therefore, one should change the hierarchy and resort to alternative schemes and/or approaches to break or overcome this barrier. We propose a scheme that uses the concept of extended surface or fin array assembly to address this problem. In our approach, we propose to back etch the silicon substrate in the form of fins of various shapes to provide additional surface area for heat conduction between the chip and the copper spreader. We present here a preliminary feasibility study that shows nearly an order of magnitude improvement in the thermal resistance of the interfaces using this innovative concept. In addition, we performed thermal modeling and optimization to derive the optimal form of fin shapes and dimensions, which provide maximum heat transfer for conduction between the silicon chip and the copper spreader.