An electrode-impedance-aware neurostimulator IC that achieves low-power consumption and fast charge balance

Abstract

Implantable neural stimulation is becoming increasingly popular for treating neurologically impaired patients, restoring neural functions which would otherwise be lost due to diseases or injuries. The charge balance of the stimulus pulses is of paramount importance for the long-term safety of the electrode-tissue interface. This paper presents a novel neurostimulator integrated circuit in which two novel charge balancing schemes are proposed. One is based on acquiring the access resistance part (RS) of the inter-electrode impedance. Thanks to its adaptive anodic phase, the RS-based charge balance circuit does not require an additional discharge phase, achieving faster charge balance than most existing stimulator ICs. The other scheme is based on acquiring the double-layer capacitance part (CDL) of the inter-electrode impedance and the entire charge balancing process (inc. monitoring, computation and compensation) is performed in the analog domain. This is in sharp contrast to the existing electrode-impedance-aware charge balancing schemes which require ADCs and compute the net charge in the digital domain. Hence the new impedance-aware charge-balancing scheme is faster and more power friendly. The impedance-aware stimulator ASIC has been implemented using X-FAB’s 180-nm CMOS process. The post-layout simulation results suggest a good charge balance is achieved as the voltage deviation from the electrode offset voltage on the electrode after the charge compensation reduces to 2.64 mV and –1.39 mV under the RS-based and CDL-based charge balancing schemes, respectively. The additional power overhead due to the proposed CDL-based charge balancer circuit is 2.46 μW at a stimulation rate of 400 Hz.