An ELDC-Free 2.78mW 20MHz-BW 75.5dB-SNDR 4th- Order CTSDM Facilitated by 2nd-Order CT NS-SAR and AC-Coupled Negative-R

Abstract

Continuous-time (CT) SDMs inherent anti-aliasing and the relatively high and constant input impedance feature, easing the ADC driver design when compared with its discrete-time (DT) counterparts. While in a hybrid structure with a DT noise-shaping SAR (NS-SAR) quantizer (OTZ), the efficiency of CTSDMs can further improve [3] [4]. However, the necessitation of the excess loop delay (ELD) compensation (ELDC) in CTSDMs poses additional power overhead. Especially, the NS-SAR OTZ performs multiple bit quantization and integration in series, requires a substantial delay ($\mathrm{t}_{\mathrm{d}}$) compensation, leading to a power-hungry loop filter. Poor compensations in highorder designs also deteriorate the in-band noise floor and even cause loop instability. As depicted in Fig.1, the compensation generally is accomplished with a fast feedback path from the OTZ’s output to input, which can be done in a number of ways [1] [2] [3] [4]. Conventional ELDC exploits an additional summing amplifier with a direct feedback ELD DAC [1], thus being energy inefficient. in [2] [3], ELDC is embedded into the integrator, saving the feedback DAC and the amplifier; but simultaneously demanding power-hungry lntegrators with higher specifications. The implementation of the ELDC can happen inside the DAC of the SAR OTZ [4]; however, this implies an additional operation phase and undesired load for the integrator. This paper proposes an ELDC-free CTSDM facilitated by a CT-NS SAR OTZ. incorporating a single amplifier biquad (SAB) and an AC+DC negative-R technique, the prototype reaches 75. 5dB SNDR with 20MHz bandwidth (BW) and 2. 78mW power, yielding a Walden Figure-of-merit (Fo$\mathrm{M}_{\mathrm{W}}$) and a Schreier FoM (FOMs) of 14.3 fJ/conversion-step and 174.1dB, respectively.