An EIC on PIC packaging solution for photonic engine of 800G data rate and beyond

Abstract

Silicon photonic is a very popular method to meet the massive increase of bandwidth and the lower power consumption demands for data centers and high-performance computing. One of the main challenges on adoption of it in data centers is the packaging which integrates both electronics integrated circuits (EICs) and the photonics integrated circuits (PICs). A careful packaging solution should be developed for higher data rate, or improper integration can negate all the possible benefit of silicon photonic. Here, we propose a novel 3D sandwich-like packaging solution which use an interposer to connect PIC and a commercial EIC attached to the front-side and back-side of it. Once a 400G data rate photonic engine is designed, it is convenient to scale it up to 800G and beyond. Then, we analyze the performance of interconnect from PCB to EIC and from EIC to PIC by simulation. We also study some impact caused by this packaging method such as travelling wave modulator's RF electrode impedance shift and crosstalk between modulator's different channel.