An Efficient Weighted-Round-Robin Algorithm for Multiprocessor Architectures

Abstract

Complex System-on-Chip (SoC) architectures comprise multiple master and slave modules. Master modules such as processors and hardware accelerators send requests or data to slave modules, e. g. memories and register banks. Efficient communication among master and slave modules requires adequate on-chip interconnect architectures with arbitration that features contention resolution, prioritization, and fairness. In this paper we present a new arbitration method with a parameterizable algorithm, such that the arbitration for each shared resource can be optimized to the traffic patterns, target characteristics, and quality-of-service requirements. We use a weighted-round-robin algorithm that takes these properties into account. As our simulations show we can improve the overall system performance of a multiprocessor SoC by up to 41%.