An efficient timing simulation approach for CMOS digital circuits

Abstract

A delay calculation method based on analytic macromodel equations is proposed for fast timing simulation of CMOS digital circuits. The delay equations are derived based on the characteristic equations of transistors of a simple inverter macromodel which include loading capacitance and input waveform slew rate. The equations are used to calculate the delay times as well as generate analytic output waveforms during simulation. The delay equations have been implemented in a mixed-mode simulator and simulation results show that the proposed delay equations can predict the delay times within 5% error for the several circuits tested, as compared with the SPICE simulation. >