An Efficient Technique for Pipelined SAR ADC with Dynamic Bulk Biasing Design

Abstract

Pipelined ADCs are becoming increasingly prevalent in SOC design, both as standalone parts and integrated functional units. The ADC employs a novel method that includes sub-ranging in a pipelined SAR and sub-binary DACs. To obtain the resolution in a traditional SAR architecture, we demand the low thermal noise by the comparator than the quantization noise in ADC. The pipelined design in this study reduces the comparator's noise requirements. To maintain gain constant across process and temperature changes, the architecture includes an open-loop integrator-based gain stage with a unique background gain calibration technique. However, with DACs, load capacitance mismatch must be resolved. An enhanced linearity bootstrapped switch design for a successive approximation register (SAR) ADC is presented in this article. The input range is 1.2V full-scale. To increase the linearity of the input signal-related transistors, a dynamic biasing circuit is used to deprive of the bulk effects. We also showed a dependable clock doubling circuit in this work. Depending on the clock doubling circuit, the transistors in the proposed circuit do not have node voltages greater than the required supply voltage. In addition, just three transistors and one capacitor are needed.