Abstract
Achieving a high decoding throughput using a successive cancellation list (SCL) decoder for polar codes is difficult due to its sequential decoding architecture. In this work, combining the local sorter from a single parity check (SPC) node with a shift-based path memory, a modified fast simplified successive cancellation list (Fast-SSCL) decoder is proposed, in order to provide a high-throughput using a low-complexity implementation. The proposed modified Fast-SSCL decoder can be operated at 470 MHz and was synthesized with an area of 5.26 mm<sup>2</sup> using a TSMC 90 nm CMOS process. The decoder presented in this work is able to improve the throughput to area ratio (TAR) by more than 30% compared with the previous designs.
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