Abstract
Mathematical modifications have been made to the Izhikevich Neuron Model to allow for a simple, low-area digital hardware implementation with low computational intensity. The implemented neuron circuit only requires one input parameter to replicate all of the cortical neuron behaviours described by Izhikevich. The low hardware requirements of this neuron implementation make large, highly parallel digital spiking neural networks of this neuron feasible. Additionally, the model requires fewer external parameter changes to exhibit diverse neuron behaviours. The alterations made to create this novel model are presented in detail with a performance comparison to the original Izhikevich Neuron. Subsequently a digital hardware realization is presented and its performance is characterized.
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