Abstract
An efficient self post package repair algorithm using on-chip-ECC is proposed and the circuit implementation details are presented. The proposed algorithm identifies and stores the addresses of hard fault detected by on-chip-ECC during post package test phase and performs subsequent repairs with changing supply voltage level controlled by tester. A yield improvement by 1~1.5% is expected and the efficiency of test and repair steps is enhanced by about 58~67%. The chip size overhead for its implementation is estimated to be under 0.4% for an 80 nm 1 Gb memory.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
