An efficient reliability simulation tool for lifetime-aware analog circuit synthesis

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Time-dependent degradation (aging) has become more severe in modern CMOS technologies. Therefore, it is highly critical to capture the variation effects and design reliable circuits against aging. Simulation of time-dependent variations is quite complicated since the degradation is a function of time, where the step count of simulation directly affects the accuracy and the efficiency of the analysis. Commercial simulator tools use a constant step count during reliability simulations, in which choosing a large step count degrades the efficiency whereas keeping it small may result in accuracy problems. To overcome this bottleneck, a couple of different approaches have been proposed in the literature. Nevertheless, they suffer from the initial workload during step count determination and some other accuracy problems. In this study, a two-level step count determination approach is presented, in which the step count induced estimation error can be promptly determined via an effective simulation strategy at the first level. At the second level, the error is fitted into a saturated power law model; thus, the efficient step count can be determined without any simulation effort. To demonstrate the developed tool, two case study circuits have been designed using 130 nm technology parameters. According to the simulation results, the proposed approach decreases the initial workload by up to 67%. The proposed approach provides a remarkable save in computation time and can be used for all analog circuits without loss of generality. Moreover, a reliability-aware analog circuit synthesis tool is implemented to demonstrate the efficiency of the proposed approach. The developed tool provides a 37% improvement in the computation time compared to the only tool in the literature.