Abstract
In the design of memristive chips, memristor models are needed to evaluate the correctness of circuit design and simulation. Although numerous memristor models exist, they are usually too complicated to exhibit satisfactory simulation speed in large-scale arrays, or too concise to accurately reflect device characteristics. In this article, we propose a PieceWise linear (PWL) memristor model with well-balanced simulation speed and accuracy. The model has continuous state equation and contains only elementary operations to guarantee the simulation efficiency. The model parameters are derived with the minimum mean square error (MMSE) fitting method from the measured data. Simulation results illustrate that, with similar fitting accuracy, our model can reduces simulation time by 30% and memory usage by 11% than state-of-the-art models in a pure network with over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times 10^{4}$ </tex-math></inline-formula> memristors. The effectiveness of this model is also validated in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$32\times 64~1$ </tex-math></inline-formula> T1R array with weight update and signal processing operations.
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