An efficient low power NoC router architecture design

Abstract

Network-on-Chip (NoC) architecture represents a promising design paradigm to cope with increasing communication requirements in digital systems. Network-on-chip (NoC) has been emerged as a keen factor that determines the performance and power consumption of many core systems. VLSI technology is used to modify NOC internal router arrangements, shortest path allocation process and neighbor router estimation control. In this architecture, our work is to design a 4∗4 mesh topology based network on chip architecture using VCS technique. This work is to optimize the path allocation processing time and to increase NOC architecture performance level. Existing system is to design a mesh topology based network on chip architecture. This architecture is to implement the circuit switching and packet switching for path allocation process. Existing packet switching process is to identify the router availability for mesh topology based NOC architecture design and circuit switching process is used to identify the path availability for mesh topology NOC architecture. Existing system is to optimize the path allocation time and to effectively transmit the source to destination processing time level. Existing time is to increase the circuit complexity level and it consume more time for circuit analysis process. Proposed system is to design a mesh topology based router architecture design and to optimize the path allocation process using hybrid scheme. This scheme is to consist of VCS, CS, PS technique for path allocation work. The proposed system reduces the data transferring time between source and destination. Proposed system is to implement the weighted distance based VCS technique and this technique is to optimize the internal path selection work. Proposed system is to implement the master and slave router condition for single router data transfer process and to optimize the path selection complexity level. This proposed architecture is to optimize the internal connectivity level and to reduce path allocation process level. This technique is to reduce data transfer time between source and destination. Proposed system is to increase the system speed level i.e the clock frequency. Proposed system is to reduce the delay time level and to reduce the latency time.