An Efficient Inter-FPGA Routing Exploration Environment for Multi-FPGA Systems

Abstract

Field programmable gate arrays (FPGAs) have seen a huge evolution since their inception almost three decades ago. Multi-FPGA boards continuously receive an increasing attention by the research community as efficient solutions for complex system prototyping. This is due to reliable high-speed, low-cost, and real-life exploration environment they offer. Although multi-FPGA platforms offer better frequency compared to other prototyping alternatives, expanding logic resource to I/O ratio in FPGAs is causing an increase in time multiplexing ratio of inter-FPGA signals (logical signals) to inter-FPGA tracks (physical resources), which causes a decline in overall system frequency. This paper introduces a generic testing platform for multi-FPGA modeling. With this platform, users will be able to experience overall prototyping cycle of a digital system. The cycle will start from benchmark generation and will go all the way to inter-FPGA routing. Using generic tools of this platform, we explore the effect of three different inter-FPGA routing approaches on the frequency of final prototyped design. Each routing approach is applied on generic as well as custom multi-FPGA boards. Results obtained through experimentation show that, for generic FPGA board, routing approach better exploiting two- and multi-point tracks of target FPGA board gives better average frequency results as compared to other two routing approaches.