An Efficient Implementation of the Sign LMS Algorithm Using Block Floating Point Format

Mrityunjoy Chakraborty,Moon Ho Lee,Rafiahamed Shaik

doi:10.1155/2007/57086

Abstract

An efficient scheme is presented for implementing the sign LMS algorithm in block floating point format, which permits processing of data over a wide dynamic range at a processor complexity and cost as low as that of a fixed point processor. The proposed scheme adopts appropriate formats for representing the filter coefficients and the data. It also employs a scaled representation for the step-size that has a time-varying mantissa and also a time-varying exponent. Using these and an upper bound on the step-size mantissa, update relations for the filter weight mantissas and exponent are developed, taking care so that neither overflow occurs, nor are quantities which are already very small multiplied directly. Separate update relations are also worked out for the step size mantissa. The proposed scheme employs mostly fixed-point-based operations, and thus achieves considerable speedup over its floating-point-based counterpart.

Highlights

Sufficient signal-to-quantization noise ratio over a large dynamic range is a desirable feature of modern day digital signal processing systems
We extend the philosophy used in [7] for a block floating point (BFP) realization of the sign LMS algorithm [13]
The sign LMS algorithm is presented in a BFP framework that ensures simple fixed point (FxP)-based operations in most of the computations while maintaining an floating point (FP)-like wide dynamic range via a block exponent

Summary

INTRODUCTION

Sufficient signal-to-quantization noise ratio over a large dynamic range is a desirable feature of modern day digital signal processing systems. While the floating point (FP) data format is ideally suited to achieve this due to normalized data representation, the accompanying high processing cost restricts its usage in many applications This is specially true for resource-constrained contexts like batteryoperated low power devices, where custom implementations on FPGA/ASIC are the primary mode of realization. The proposed scheme adopts appropriate BFP format for the filter coefficients which remains invariant as the coefficients are updated in time Using this and the BFP representation of the data as used in [7], separate time update relations for the filter weight mantissas and the exponent are developed.

THE BFP ARITHMETIC AND A BLOCKFORMATTING ALGORITHM

THE PROPOSED IMPLEMENTATION

COMPLEXITY ISSUES

SIMULATION AND FINITE PRECISION IMPLEMENTATION

CONCLUSION