An efficient implementation of novel Paillier encryption with polar encoder for 5G systems in VLSI

Abstract

In this paper, a novel design of Paillier encryption with a modified polar encoding is proposed and analyzed. A new cross-partitioned add shift processing element based on perfect reconstruction technique is designed for the realization of encryption with proper distribution of adders and shifters to minimize the logical component and register usage. In addition, a modified architecture for the polar encoder with optimal delay/ minimized hardware resource is achieved by presenting a novel delay calculation methodology followed by register allocation grouped as the Reduced Register Delay Allocation (RRDA) algorithm. Resource utilization, including slice registers, lookuptables (LUTs) and DSP blocks are measured along with operating speed and throughput for the proposed paillier encryption and polar encoder. Finally, the performance is analyzed with the existing designs. The proposed sequential encoding-encryption can be deployed in imminent 5G systems.