An efficient implementation of montgomery powering ladder in reconfigurable hardware

Abstract

This paper describes an efficient architecture to perform modular exponentiation using the Montgomery Powering Ladder algorithm. The implementation is composed by two parallel modular multiplication modules in order to speed-up the modular exponentiation time. The modular multiplication architecture is high-radix and presents an one-dimensional array of processing elements within multiplexed multipliers. This architecture can performs the 1024 bits RSA decryption in 2.5 ms. Furthermore, the modular exponentiation architecture presents a countermeasure against SPA attack.