Abstract
SummaryImage compression is significant for resourceful transmission and storage of images. The multimedia data like image, audio, and videos are uploaded in the Internet through telecommunication networks. Actual image size plays when page utilization is higher. So image compression standard joint photographic experts group (JPEG) is used for storing images in a compressed format. The quality of JPEG is that it yields little loss in quality using high compression ratios. Multiplier and adder play a major hardware resource in JPEG compression. To reduce this, hardware complexity here proposed a compressor‐based multiplier to increase the performance of JPEG standard as well as reducing the logic resources. This architecture is going to be implemented in CYCLONE IV FPGA with 512 × 512 and 640 × 480 resolutions of images.
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