An efficient image compression architecture based on optimized 9/7 wavelet transform with hybrid post processing and entropy encoder module

Abstract

Satellite communication is popular due to the advancement in storing and transmitting satellite images. Image compression can be defined as the science of lowering the number of bits necessary to represent an image. In satellite image processing, image degradation is considered a challenging problem. The Consultative Committee for Space Data Systems (CCSDS) Image Data Compression (IDC) standard CCSDS-122.0-B-1 is the transformation-dependent image compression method developed especially for usage in on-board space platforms. It holds de-correlation, quantization and entropy encoding phases. This paper introduces a new optimized memory organization for Discrete Wavelet Transform (DWT) to perform spatial de-correlation with fewer memory requirements on an FPGA device. Also, the proposed optimized DWT is integrated with a hybrid post-processing and entropy encoder module to reduce the spatial redundancies between the wavelet coefficients and compress the de-correlated data with high compression performance. A high-throughput hardware implementation of the Binary arithmetic entropy Coder (BAEC) is also provided to perform lossless compression with low implementation complexity. To provide the convenience and compactness, the proposed system will be implemented in the Xilinx working platform by developing a Verilog code. The proposed model is then evaluated on the Arty Z7–20 development board. The proposed approach is analyzed on different performance parameters such as throughput and frequency. The proposed design allowed a maximum operating frequency of 250 MHz, leading to a throughput of 156.25 Msamples/sec on Zynq. In addition, the structure of the proposed method overtakes the conventional design in terms of memory requirements and area.