An efficient high speed Wallace tree multiplier

Abstract

Power dissipation of integrated circuits is a major concern for VLSI circuit designers. A Wallace tree multiplier is an improved version of tree based multiplier architecture. It uses carry save addition algorithm to reduce the latency. This paper aims at further reduction of the latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of 4∶2, 5∶2 compressors and a proposed carry select adder. The result shows that the proposed Wallace tree multiplier is 44.4% faster than the conventional Wallace tree multiplier, along with realization of 11% of reduced power consumption. The simulations have been carried out using the Modelsim and Xilinx tools