An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks.

Huan-Yuan Chen,Wen-Jyi Hwang,Chih-Chang Chen

doi:10.3390/s17102232

Huan-Yuan Chen, Wen-Jyi Hwang + Show 1 more

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https://doi.org/10.3390/s17102232

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Abstract

This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

Highlights

Multi-electrode arrays (MEAs) [1,2] are sensors capable of recording spike data from a large number of neurons of the brain simultaneously
The MEAs have been extensively deployed to facilitate the development of applications such as brain-machine interface (BMI) and/or neuromotor prosthetic devices [3,4] for the rehabilitation of stroke or paralyzed patients
The objective of this paper is to present a novel spike sorting hardware architecture supporting spike detection, feature extraction and classification

Summary

Introduction

Multi-electrode arrays (MEAs) [1,2] are sensors capable of recording spike data from a large number of neurons of the brain simultaneously. The MEAs have been extensively deployed to facilitate the development of applications such as brain-machine interface (BMI) and/or neuromotor prosthetic devices [3,4] for the rehabilitation of stroke or paralyzed patients. For the MEA-based applications, multi-channel spike sorting [5,6] is usually desired. The spike sorting aims to segregate spikes of individual neurons from the data acquired from each channel. It can be viewed as a clustering process where the spikes belonging to the same neuron are grouped together. The information of the clustering results provided by the spike sorting is essential to the subsequent operations such as neural decoding and control signal generation for prosthetic devices [4]

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