Abstract

The SMS4 cryptosystem has been used in the Wireless LAN Authentication and Privacy Infrastructure (WAPI) standard for providing data confidentiality in China. So far, reliability has not been considered a primary objective in original version. However, a single fault in the encryption/decryption process can completely change the result of the cryptosystem no matter the natural or malicious injected faults. In this paper, we proposed low-cost structure-independent fault detection scheme for SMS4 cryptosystem which is capable of performing online error detection and can detect a single bit fault or odd multiple bit faults in coverage of 100 percent. Finally, the proposed techniques have been validated on Virtex-7 families FPGA platform to analyze its power consumption, overhead and time delay. It only needs 85 occupied Slices and 8.72mW to run a fault-tolerant scheme of SMS4 cryptosystem with 0.735ns of detection delay. Our new scheme increases in minimum redundancy to enhance cryptosystem’s reliability and achieve a better performance compared with the previous scheme.

Highlights

  • With the rapid development of network and digitization, the information protection has nowadays became an absolutely requirement

  • In this paper we did some research on the SMS4 cryptosystem of fault detection

  • We showed the traditional scheme of error detective method on SMS4 and presented a new fault detection scheme based on parity code

Read more

Summary

Introduction

With the rapid development of network and digitization, the information protection has nowadays became an absolutely requirement. A scheme is put forward in [7], which used reverse functions to recover the original input for the encryption/decryption process; [8,9] can applied to the internal function, round function, or entire encryption process levels, based on the hardware-redundant-based concurrent error detection schemes. Another category of fault detection methods is based on parity codes [10,11,12].

Description of SMS4 algorithm
Error model
Fault detection techniques
B 18 I B 24
Fault detection rate
FPGA implementations and comparison
Findings
Conclusion

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.