Abstract
In this paper, a new fast inverse modified discrete cosine transform (IMDCT) algorithm and an efficient hardware accelerator architecture are proposed. The proposed fast algorithm is derived from our previously presented type-IV discrete cosine transform/type-IV discrete sine transform (DCT-IV/DST-IV) decomposition algorithm. After transformations of DST-IV to DCT-IV and DCT-IV to IDCT-II, the computational items are further recombined to share hardware resources. Experimental results show that the proposed algorithm's computational cycles are decreased by 20% and 51%, respectively compared with two other reported fast algorithms. By employing resource sharing and multiplexing techniques, the proposed hardware accelerator reduces 24% and 48% of transistors compared with two other ones, respectively.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.