An Efficient FPGA-Based Accelerator for Perceptual Weighting Filter in Speech Coding

Abstract

In speech coding, denoising of the speech signal is essential as well as crucial. The filters for minimizing errors through denoising employ the autoregressive moving average (ARMA) approach, introducing higher computational complexity in speech coder design. This research work presents the design and implementation of an effective perceptual weighting filter (PWF) for speech coding. The high-level synthesis of the fixed-point PWF filter is optimized by multiple optimization techniques along with detailed design space exploration using the weighted sum (WS) method. To enhance the performance, an FPGA-based hardware accelerator is proposed using hardware/software (HW/SW) co-design in an embedded environment. Simulative analysis in Vivado HLS and final accelerator design in the Vitis IDE tool validate the proposed architecture by using real-time speech samples, demonstrating a 50% reduction in area and a 99% execution improvement. This makes it well-suited for use in modern speech codecs, enhancing the efficiency.