Abstract
NAND Flash memories, due to their several desirable characteristics, have recently dominated the storage technology and its global market. Multi-level cell (MLC) Flash memories, which have higher storage capacities as each cell contains more than one bit of data, have gained considerable amount of attention and researches to build smaller and denser memory cells continue. Studies have shown that, among various error sources in MLC memories, inter-cell interference is the significant one. Therefore, simple, feasible, and yet effective equalization techniques are vital for data reliability. In this paper, we have analyzed the error performance of the proposed effective equalizer, while low- density parity-check error control scheme has also been utilized to construct a joint equalization-coding scheme.
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