An Efficient Dynamically Reconfigurable Fir Filter Using Multiprecision Razor Based Multiplier with Frequency Scaling

Abstract

This paper presents a multiprecision (MP) dynamic and partially reconfigurable fir filter that incorporates variable precision, parallel processing (PP) multiplier, razor-based error detection, dynamic frequency scaling and dedicated operands scheduling to give optimum performance for a variety of operating conditions. Each of the building blocks of the proposed architecture can either work as independent smallerprecision systems or work in parallel to execute higher-precision system. Our aim is to realize a less-delay; area-efficient reconfigurable digital signal processing design that is implemented using Xilinx Synthesis Tool on Virtex5 FPGA kit. The proposed design provides area efficiency and flexibility by permitting dynamically insertion and/or removal of the individual modules to execute various taps for the partial reconfigurable FIR filters. The FIR Filters are being designed using HDL languages since speed is an important interest in this era; the main objective is to improve the speed of the system. In the whole system if the speed of the individual block is improved the overall speed of the system is enhanced. The synthesis results show that the proposed MP design features a minimum-delay and also a reduction in circuit area when compared with reconfigurable fir filter using conventional fixed-width multiplier.