An efficient design method for optimal MOS integrated circuit switched-capacitor LDI ladder filters

Abstract

An optimization-based technique is presented for the design of SC-ladder filters derived from lossless discrete integrator (LDI) structures. LDI SC filters have a number of attractive features, including low sensitivity and ready availability of prototype design data, but suffer from certain errors of approximation inherent in their realization. Capacitance spread can become large in dealing with these errors by conventional methods, and this is then a serious difficulty when integrated circuit realization is attempted. The present design technique eliminates this problem via numerical optimization. The procedure also allows the designer to compensate for the effect of the non-ideal characteristics of practical MOS components including finite gain-bandwidth in the op amps. The technique allows for the use of relatively low sampling frequencies and results in a low-sensitivity filter having an exact frequency response and featuring very low on-chip capacitance spread. >