Abstract
An efficient degraded deductive simulator for small delay defects is proposed. The proposed method takes into account the conditions of re-convergence sensitization and hazard-based detection, providing fast and accurate simulation results for small delay defects. Separate simulation strategies for faults with different fault effects are proposed. For faults on fault effects re-convergent fan-out stems, the serial simulation technique is applied. For other faults, a deductive simulation technique is proposed to accelerate the simulation. Different from previous works, serial simulations are carried out no longer for all faults on fan-out re-convergent stems, but only for fault effects re-convergences, and the other faults are parallel simulated with the degraded deductive technique, which eliminates “AND” operation and the propagation of fault-list is simpler than conventional deductive ones. Experimental results demonstrate that the proposed simulator that can further accelerate the fault simulation in efficiency. It achieves a 28.3X speedup on average compared with the serial simulation method, and a 3.92X speedup on average compared with the critical path tracing based method.
Highlights
Integrated circuit (IC) testing is a necessary part of chip production
As only the interval between the earliest arrival time (EAT) and the latest stabilization time (LST) needs to be considered [19], the actual waveform s can be expressed by EAT(s)=2, and Bitmap(s) = 001011B, where the initial state is recorded in the first bit, the following bits record the states of V2 beginning from time EAT(s)=2 to time LST(s)=6
In order to accelerate the speed of small delay defect (SDD) simulation, an efficient small delay fault simulator is proposed
Summary
Integrated circuit (IC) testing is a necessary part of chip production. Empirical data proves that as the chip size shrinking, more and more failures are skewed towards smaller delays [1]. Path-delay based simulations [12,13,14,15,16] record the lengths of sensitized paths for timing expression, where the fault detection interval is determined by the maximum sensitized path length. Full-waveform based fault simulations [18,19,20,21] accurately simulate the timing information. In [21], a critical path tracing technique is applied to small-delay fault simulation, which makes a fast judgment and significantly accelerates the process of simulation. The idea of deductive simulation is applied to SDD simulation, with the consideration of re-convergent sensitization and hazardbased detection. For faults on fault effects re-convergent fan-out stems, the serial simulation technique is applied.
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